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Espressif Systems /ESP32-S2 /PCNT /CTRL

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Interpret as CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CNT_RST_U0)CNT_RST_U0 0 (CNT_PAUSE_U0)CNT_PAUSE_U0 0 (CNT_RST_U1)CNT_RST_U1 0 (CNT_PAUSE_U1)CNT_PAUSE_U1 0 (CNT_RST_U2)CNT_RST_U2 0 (CNT_PAUSE_U2)CNT_PAUSE_U2 0 (CNT_RST_U3)CNT_RST_U3 0 (CNT_PAUSE_U3)CNT_PAUSE_U3 0 (CLK_EN)CLK_EN

Description

Control register for all counters

Fields

CNT_RST_U0

Set this bit to clear unit 0’s counter.
CNT_PAUSE_U0

Set this bit to freeze unit 1’s counter.
CNT_RST_U1

Set this bit to clear unit 2’s counter.
CNT_PAUSE_U1

Set this bit to freeze unit 3’s counter.
CNT_RST_U2

Set this bit to clear unit 4’s counter.
CNT_PAUSE_U2

Set this bit to freeze unit 5’s counter.
CNT_RST_U3

Set this bit to clear unit 6’s counter.
CNT_PAUSE_U3

Set this bit to freeze unit 7’s counter.
CLK_EN

The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data